MSPI external RAM ECC and SPI CS timing control register
| SPI_SMEM_CS_SETUP | For SPI0 and SPI1, spi cs is enable when spi is in prepare phase. 1: enable 0: disable. |
| SPI_SMEM_CS_HOLD | For SPI0 and SPI1, spi cs keep low when spi is in done phase. 1: enable 0: disable. |
| SPI_SMEM_CS_SETUP_TIME | For spi0, (cycles-1) of prepare phase by spi clock this bits are combined with spi_mem_cs_setup bit. |
| SPI_SMEM_CS_HOLD_TIME | For SPI0 and SPI1, spi cs signal is delayed to inactive by spi clock this bits are combined with spi_mem_cs_hold bit. |
| SPI_SMEM_ECC_CS_HOLD_TIME | SPI_SMEM_CS_HOLD_TIME + SPI_SMEM_ECC_CS_HOLD_TIME is the SPI0 and SPI1 CS hold cycles in ECC mode when accessed external RAM. |
| SPI_SMEM_ECC_SKIP_PAGE_CORNER | 1: SPI0 skips page corner when accesses external RAM. 0: Not skip page corner when accesses external RAM. |
| SPI_SMEM_ECC_16TO18_BYTE_EN | Set this bit to enable SPI0 and SPI1 ECC 16 bytes data with 2 ECC bytes mode when accesses external RAM. |
| SPI_SMEM_CS_HOLD_DELAY | These bits are used to set the minimum CS high time tSHSL between SPI burst transfer when accesses to external RAM. tSHSL is (SPI_SMEM_CS_HOLD_DELAY[5:0] + 1) MSPI core clock cycles. |
| SPI_SMEM_SPLIT_TRANS_EN | Set this bit to enable SPI0 split one AXI accesses EXT_RAM transfer into two SPI transfers when one transfer will cross flash/EXT_RAM page corner, valid no matter whether there is an ECC region or not. |